PLDI 2025
Mon 16 - Fri 20 June 2025 Seoul, South Korea

This program is tentative and subject to change.

Thu 19 Jun 2025 14:40 - 15:00 at Grand Ball Room 2 - Architecture

Compared to familiar hardware-description languages like Verilog, rule-based languages like Bluespec offer opportunities to import modularity features from software programming. While Verilog modules are about connecting wires between submodules, Bluespec modules resemble objects in object-oriented programming, where interactions with a module occur only through calls to its methods. However, while software objects can typically be characterized one method at a time, the concurrent nature of hardware makes it essential to consider the repercussions of invoking multiple methods simultaneously. Prior formalizations of rule-based languages conceptualized modules by describing their semantics considering arbitrary sets of simultaneous method calls. This internalized concurrency significantly complicates correctness proofs. Rather than analyzing methods one-at-a-time, as is done when verifying software object methods, validating the correctness of rule-based modules necessitated simultaneous consideration of arbitrary subsets of method calls. The result was a number of proof cases that grew exponentially in the size of the module’s API.

In this work, we side-step the exponential blowup through a set of judicious language restrictions. We introduce a new Bluespec-inspired formal language, Fjfj, that supports sequential characterization of modules, while preserving the concurrent hardware nature of the language. We evaluated Fjfj by implementing it in Coq, proving the key framework principle: the refinement theorem. We demonstrated Fjfj’s expressivity via implementation and verification of three examples: a pipelined processor, a parameterized crossbar, and a network switch.

This program is tentative and subject to change.

Thu 19 Jun

Displayed time zone: Seoul change

14:00 - 15:00
14:00
20m
Talk
Ripple: Asynchronous Programming for Spatial Dataflow Architectures
PLDI Research Papers
Souradip Ghosh Carnegie Mellon University, Yufei Shi Carnegie Mellon University, Brandon Lucia Carnegie Mellon University, Nathan Beckmann Carnegie Mellon University
DOI
14:20
20m
Talk
Circuit Optimization using Arithmetic Table Lookups
PLDI Research Papers
Raghav Malik Purdue University, Vedant Paranjape Purdue University, Milind Kulkarni Purdue University
DOI
14:40
20m
Talk
Making Concurrent Hardware Verification Sequential
PLDI Research Papers
Thomas Bourgeat EPFL, Jiazheng Liu Massachusetts Institute of Technology, Adam Chlipala Massachusetts Institute of Technology, Arvind Massachusetts Institute of Technology
DOI
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